AndesCore™ AX46MP(V)
2 different packages with or without vector: AX46MPV, AX46MP
in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
Symmetric multiprocessing up to 16 cores
Private Level-2 cache
Shared L3 cache and coherence support
Dual scalar and vector load/store unit
Enhanced sharable High bandwidth vector local memory (HVM)
AndeStar™ V5 Instruction Set Architecture (ISA)
Compliant to RISC-V GCBPV + CMO extensions
Andes performance extension
Andes CoDense™ extension for further compaction of code size
RVA22 support
Separately licensable Andes Custom Extension™ (ACE) for customized scalar and vector instruction
Dynamix UXL feature support 64bit OS with 32bit Applications on the same core
Branch predication to speed up control code
Linux-capable Memory Management Unit (MMU)
Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PPMA)
Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
Multiprocessing up to 16 cores with hardware managed data coherence
Configurable VPU vector length (VLEN) and datapath length (DLEN)
BF16 full arithmetic mode for scalar and vector
Andes Matrix Multiply Extension for fast matrix multiply computation
Platform-Level Interrupt Controller (PLIC) support with easy arrangement of preemptive interrupts
ECC or Parity for SRAM error protection
StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
Versatile configurations to tradeoff between core size and performance requirements
PowerBrake and WFI (Wait For Interrupt) for different power saving occasions