AndesCore™ D45-SE
32-bit in-order dual-issue 8-stage pipeline CPU architecture
AndeStar™ V5 Instruction Set Architecture (ISA)
Compliant to RISC-V RV32 GCBP little endian:
RV-GC: Integer, single/double precision floating point and 16-bit extensions
RV-B Bit manipulation extensions
RV-P (draft) DSP/SIMD extensions
Andes V5 performance/code size extensions
16/32-bit mixable instruction format for compacting code density
Advanced low power branch predication to speed up control code
Return Address Stack (RAS) to accelerate procedure returns
Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
MemBoost for heavy memory transactions
Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
Enhancement of vectored interrupt handling for real-time performance
Advanced CoDense™ technology to reduce program code size